FIG. 19 is a diagram for explaining a typical configuration example of a decoder circuit of a data driver that selects a voltage (grayscale voltage) from a plurality of reference voltages based on an image data signal and supplies the selected voltage to a display element in a display panel. In FIG. 19, for the sake of simplification of the explanation, there is shown an example in which the image data signal is a 3-bit digital signal (its High level is a high-potential power supply VDD and its Low level is a low-potential power supply VSS), and the 3-bit data signal and its complementary signal D1/D1B, D2/D2B, and D3/D3B select one voltage from eight reference voltages V1 to V8 in a tournament scheme and output the selected voltage. In other words, the decoder circuit comprises 14 PMOS transistors (pass transistors) that function as switches (transfer gates) which are controlled to be turned on and off by D1/D1B, D2/D2B, and D3/D3B supplied to their gates, and which output the selected voltage when turned on. The magnitude relationship among the high-potential power supply VDD, the low-potential power supply VSS (for instance GND (ground) potential), and the eight reference voltages V1 to V8 is as follows:VDD≧V1>V2>V3> . . . >V8≧VSS. 
In the configuration shown in FIG. 19, when D1, which is the LSB (the Least Significant Bit), is at a Low level (D1B, the complementary signal of D1, is at a High level), the P-channel transistors 902, 904, 906, and 908 having gates supplied with D1 are turned on, the P-channel transistors 901, 903, 905, and 907 having gates supplied with D1B are turned off, and the reference voltages V2, V4, V6, and V8 are transferred to one ends (for instance a source) of the P-channel transistors 909, 910, 911, and 912, respectively. When D1B is at a Low level (D1=High), the P-channel transistors 901, 903, 905, and 907 are turned on, the P-channel transistors 902, 904, 906, and 908 are turned off, and the reference voltages V1, V3, V5, and V7 are transferred to one ends (for instance a source) of the P-channel transistors 909, 910, 911, and 912, respectively.
When D2 is at a Low level (D2B, the complementary signal of D2, is at a High level), the P-channel transistors 910 and 912 having gates supplied with D2 are turned on, the P-channel transistors 909 and 911 having gates supplied with D2B are turned off, and the voltage V3 or V4 passing through the P-channel transistor 903 or 904 and the voltage V7 or V8 passing through the P-channel transistor 907 or 908 are transferred to one ends (for instance a source) of the P-channel transistors 913 and 914, respectively.
When D2B is at a Low level (D2=High), the P-channel transistors 909 and 911 are turned on, the P-channel transistors 910 and 912 are turned off, and the voltage V1 or V2 passing through the P-channel transistor 901 or 902 and the voltage V5 or V6 passing through the P-channel transistor 905 or 906 are transferred to one ends (for instance a source) of the P-channel transistors 913 and 914, respectively.
When D3 is at a Low level (D3B=High), the P-channel transistor 914 having a gate supplied with D3 is turned on, the P-channel transistor 913 having a gate supplied with D3B is turned off, and a voltage (any one of the voltages V5 to V8) passing through the P-channel transistor 911 or 912 is transferred to a terminal 5.
When D3B is at a Low level (D3=High), the P-channel transistor 913 is turned on, the P-channel transistor 914 is turned off, and a voltage (any one of the voltages V1 to V4) passing through the P-channel transistor 909 or 910 is transferred to the terminal 5.
The high-potential power supply voltage VDD is supplied to back gates of the PMOS transistors 901 to 914. A gate-to-source voltage when a MOS transistor is turned on, i.e., when a channel for carriers is formed (an inversion layer is formed) on a substrate surface directly below a gate oxide film, is called a threshold voltage. Since a gate-to-source voltage of a PMOS transistor has a negative value, a threshold voltage Vtp (<0) of PMOS transistor is treated as an absolute value |Vtp| in terms of magnitude relationship in the below.
A substrate bias effect will be briefly explained. As described in standard textbooks, the threshold voltage of a MOS transistor for a substrate voltage VBS is given by the following expression (1):
                              V          th                =                              V                          th              ⁢                                                          ⁢              0                                +                      Δ            ⁢                                                  ⁢                          V              th                                                          (        1        )                                          Δ          ⁢                                          ⁢                      V            th                          =                  γ          ⁡                      (                                                                                                                        2                      ⁢                                              Φ                        F                                                              +                                          V                      BS                                                                                                    -                                                                                      2                    ⁢                                          Φ                      F                                                                                                              )                                              (        2        )            
Vth0 in the expression (1) is a threshold voltage of an NMOS transistor when the substrate voltage is 0, ΔVth is the increment when the back gate voltage equals to VBS and given by the expression (2). In the expression (2), γ is a substrate bias effect coefficient and is given by the following expression (3).
                    γ        =                                            2              ⁢              q              ⁢                                                          ⁢                              ɛ                Si                            ⁢                              N                sub                                                          C            ox                                              (        3        )            
where q is the electron charge, εSi is a permeability of silicon, Nsub is an impurity concentration of the substrate and COX is a gate capacitance of a unit area. For instance, γ is approximated by 0.4V1/2 or 0.5V1/2 in most cases.
Further, ΦF in the expression (2) can be given by the following expression (4).
                              Φ          F                =                                                            E                I                            -                              E                F                                      q                    =                                    kT              q                        ⁢                          ln              ⁡                              (                                                      N                    sub                                                        n                    I                                                  )                                                                        (        4        )            
where EF is a Fermi level, EI is an intrinsic Fermi level in the midst of the gap, q is the electron charge, Nsub is an impurity concentration of the substrate, nI is a free electron density of intrinsic silicon, k is the Boltzmann Constant, and T is an absolute temperature. For instance, 2ΦF is treated as a value of approximately 0.7V.
In case of an NMOS transistor, if the back gate voltage Vbn is lowered from a source potential (for instance the GND potential), its threshold voltage Vtn will increase by ΔVth given by the expression (2) as ΔVtn, and conversely if the back gate voltage Vbn is raised from the source potential (GND potential), the threshold voltage Vtn will decrease. In case of a PMOS transistor provided on an N-type silicon substrate, if the back gate voltage is raised higher than the source potential (for instance the power supply voltage VDD), an absolute value |Vtp| of the threshold voltage will increase by ΔVth given by the expression (2), as ΔVtp. Conversely if the back gate voltage of a PMOS transistor is lowered from the power supply voltage VDD, an absolute value |Vtp| of a threshold voltage of the PMOS transistor will decrease (a reduced threshold voltage).
In the decoder shown in FIG. 19, for instance, when the Low voltage (VSS) is applied to the gates of the PMOS transistors 908, 907, 912, and 914 that select the low potential reference voltage such as V8 and V7, the potential applied to the sources of the PMOS transistors 908, 907, 912, and 914 is given as follows: V8=VSS+α or V7=VSS+β (β>α≧VSS), and the PMOS transistors 908, 907, 912, and 914 are not turned on (conductive) when their gate-to-source voltage |VGS|=|α| or |β| is less than their threshold voltage |Vtp|. Even if turned on, a propagation delay time of each of the PMOS transistors may increase and an output delay may occur. Further, a gate width (W) of a PMOS transistor needs to be increased in order to decrease an on-resistance RON thereof. This may be result in an increase of an area.
As is well known, the on-resistance RON of a MOS transistor can be given by the following expression (5).
                              R          on                =                  1                                    μ              c                        ⁢                          C              ox                        ⁢                          W              L                        ⁢                          (                                                V                  GS                                -                                  V                  th                                            )                                                          (        5        )            
where μC is a carrier mobility (electron in the case of NMOS, while hole in the case of PMOS), COX is a gate capacitance of a unit area, W is a gate width, L is a gate length, VGS is a gate-to-source voltage, and Vt is a threshold voltage. According to the expression (5), for instance increasing the gate width W, or increasing (VGS−Vth) by decreasing Vth will decrease the value of the on-resistance RON.
In the decoder shown in FIG. 19, in order for the PMOS transistors 907 and 908, which receive V8=VSS+α, or V7=VSS+β (β>α>0) at one of their ends and receive the Low level at their gates, to be turned on (electrically conductive), the threshold voltage Vtp of the PMOS transistor must be decreased.
Further, when the threshold voltage of a MOS transistor is decreased in order to widen the selectable voltage range of a decoder circuit of a data driver, a leakage current flows from an output side into the low threshold voltage MOS transistor owing to a grayscale voltage (refer to Patent Document 1). FIG. 20 is quoted from FIG. 5 of Patent Document 1 (Japanese Patent Kokai Publication No. JP-P2000-250490A). Patent Document 1 discloses the configuration in which a MOS transistor M1 arranged in the highest order of a low Vth MOS transistor (M2-M7) of a grayscale group of a decoder circuit of a drain driver to compose a CMOS transfer gate, to prevent a current from flowing from an output side into the low Vth MOS transistor by a grayscale voltage applied to another portion. In FIG. 20, in order to widen the output range of the decoder, MOS transistors M2 to M7 are lowered in Vth. Further, in order to prevent a current from flowing into the low Vth NMOS transistor (a leakage current between a drain and a source) when a reference voltage V9 is selected, the MOS transistor M1 is connected in parallel with a PMOS transistor to compose a CMOS transfer gate.    [Patent Document 1]    Japanese Patent Kokai Publication No. JP-P2000-250490A